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dc to 600 mhz, dual-digital variable gain amplifiers data sheet ad8366 rev. b document feedback information furnished by analog devices is believed to be accurate an d reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of pat ents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pa tent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2010C2017 analog devices, inc. all rights reserved. technical support www.analog.com features matched pair of differential, digitally controlled vgas gain range: 4.5 db to 20.25 db 0.25 db gain step size operating frequency dc to 150 mhz (2 v p-p) 3 db bandwidth: 600 mhz noise figure (nf) 11.4 db at 10 mhz at maximum gain 18 db at 10 mhz at minimum gain oip3: 45 dbm at 10 mhz hd2/hd3 better than ?90 dbc for 2 v p-p output at 10 mhz at maximum gain differential input and output adjustable output common-mode optional dc output offset correction serial/parallel mode gain control power-down feature single 5 v supply operation applications baseband i/q receivers diversity receivers wideband adc drivers functional block diagram vpsia ippa ipma enbl icom ipmb ippb vpsib bit0/cs bit1/sdat bit2/scl k bit3 ocom bit4 bit 5 dena deca ofsa ccma vcma vpsoa oppa opma senb decb ofsb ccmb vcmb vpsob oppb opmb denb digital gain control logic 07584-001 figure 1. general description the ad8366 is a matched pair of fully differential, low noise and low distortion, digitally programmable variable gain amplifi ers (vgas). the gain of each amplifier can be programmed separately or simultaneously over a range of 4.5 db to 20.25 db in steps of 0.25 db. the amplifier offers flat frequency performance from dc to 70 mhz, independent of gain code. the ad8366 offers excellent spurious-free dynamic range, suitable for driving high resolution analog-to-digital converters (adcs). the nf at maximum gain is 11.4 db at 10 mhz and increases ~2 db for every 4 db decrease in gain. over the entire gain range, the hd3/hd2 are better than ?90 dbc for 2 v p-p at the output at 10 mhz into 200 . the two-tone intermodulation distortion of ?90 dbc into 200 translates to an oip3 of 45 dbm (38 dbvrms). the differential input impedance of 200 provides a well-defined termination. the differential output has a low impedance of ~25 . the output common-mode voltage defaults to v pos /2 but can be programmed via the vcma and vcmb pins over a range of voltages. the input common-mode voltage also defaults to v pos /2 but can be driven down to 1.5 v. a built-in, dc offset compensation loop can be used to eliminate dc offsets from prior stages in the signal chain. this loop can also be disabled if dc- coupled operation is desired. the digital interface allows for parallel or serial mode gain programming. the ad8366 operates from a 4.75 v to 5.25 v supply and consumes typically 180 ma. when disabled, the part consumes roughly 3 ma. the ad8366 is fabricated using analog devices, inc., advanced silicon-germanium bipolar process, and it is available in a 32-lead exposed paddle lfcsp package. performance is specified over the ?40c to +85c temperature range.
ad8366 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? parallel and serial interface timing ............................................ 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? circuit description ......................................................................... 15 ? inputs ........................................................................................... 15 ? outputs ........................................................................................ 15 ? output differential offset correction .................................... 15 ? output common-mode control ............................................. 15 ? gain control interface ............................................................... 16 ? applications information .............................................................. 17 ? basic connections ...................................................................... 17 ? direct conversion receiver design ......................................... 18 ? quadrature errors and image rejection ................................. 18 ? low frequency imd3 performance ........................................ 19 ? baseband interface ..................................................................... 21 ? characterization setups ................................................................. 22 ? evaluation board ............................................................................ 25 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 8/2017rev. a to rev. b change to figure 4 ........................................................................... 7 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 28 3/2011rev. 0 to rev. a changes to table 2, internal power dissipation value ................ 6 10/2010revision 0: initial version
data sheet ad8366 rev. b | page 3 of 28 specifications v s = 5 v, t a = 25 c, z s = 200 ?, z l = 2 00 ?, f = 10 mhz, unless otherwise noted . t able 1. parameter test conditions/comments min typ max unit dynamic performance bandwidth 3 db; all gain codes 6 00 mhz 1 db; all gain codes 20 0 mhz slew rate maximum gain 1100 v/ s minimum gain 1500 v/ s input stage ippa, ipma, ippb, ipmb linear i nput swing at minimum gain a v = 4.5 db, 1 db g ain compression 3.6 v p -p differential input impedance 217 minimum input common - mode voltage 1.5 v maximum input common - mode voltage v pos /2 + 0.075 v input pins left floating v pos /2 v gain minimum voltage gain 4.5 db maximum voltage gain 20. 25 db gain step size all gain codes 0.25 db gain step accuracy all gain codes 0.25 db gain flatness maximum gain, dc to 70 mhz 0.1 db gain mismatch channel a / channel b at minimum/maximum gain code 0.1 db group delay flatness all gain codes, 20% fractional bandwidth, f c < 100 mhz <0.5 ns mismatch channel a and channel b at same gain code 2 ps gain step response maximum gain to minimum gain 30 ns minimum gain to maximum gain 60 ns common - mode rejection ratio ? 66.2 db output stage oppa, opma, oppb, opmb, vcma, vcmb linear output swing 1 db gain compression 6 v p -p differential output impedance 28 output dc offset inputs shorted, offset loop disabled at minimum/maximum gain ? 10/ ? 30 mv inputs shorted, offset loop enabled (across all gain codes) 10 mv minimum output common - mode voltage hd3, hd2 > ? 90 dbc, 2 v p - p output 1.6 v maximum output common - mode voltage hd3, hd2 > ? 90 dbc, 2 v p - p output 3 v vcma and vcmb left floating v pos /2 v common - mode setpoint input impedance 4 k noise/distortion 3 mhz noise figure maximum gain 11.3 db minimum gain 18.2 db second harmonic 2 v p - p output, maximum gain ? 82 dbc 2 v p - p output, minimum gain ? 82 dbc third harmonic 2 v p - p output, maximum gain ? 87 dbc 2 v p - p output, minimum gain ? 90 dbc oip3 1 2 v p - p composite, maximum gain 34 dbvrms 2 v p - p composite, minimum gain 35 dbvrms oip2 1 2 v p - p composite, maximum gain 76 dbvrms 2 v p - p composite, minimum gain 76 dbvrms output 1 db compression point 1 maximum gain 6.7 dbvrms minimum gain 6.9 dbvrms
ad8366 data sheet rev. b | page 4 of 28 parameter test conditions/comments min typ max unit 10 mhz noise figure maximum gain 11.4 db minimum gain 18 db second harmonic 2 v p - p output, maximum gain ? 97 dbc 2 v p - p output, minimum gain ? 96 dbc third harmonic 2 v p - p output, maximum gain ? 97 dbc 2 v p - p output, minimum gain ? 90 dbc oip3 1 2 v p - p composite, maximum gain 38 dbvrms 2 v p - p composite, minimum gain 36 dbvrms oip2 1 2 v p - p composite, maximum gain 72 dbvrms 2 v p - p composite, minimum gain 76 dbvrms output 1 db compression point 1 maximum gain 7 dbvrms minimum gain 6 .7 dbvrms 50 mhz noise figure maximum gain 11.8 db minimum gain 18.2 db second harmonic 2 v p - p output, maximum gain ? 82 dbc 2 v p- p output, minimum gain ? 84 dbc third harmonic 2 v p - p output, maximum gain ? 80 dbc 2 v p - p output, minimum gain ? 71 dbc oip3 1 2 v p - p composite, maximum gain 32 dbvrms 2 v p - p composite, minimum gain 26 dbvrms oip2 1 2 v p - p composite, m aximum g ain 71 dbvrms 2 v p - p composite, minimum gain 78 dbvrms output 1 db compression point 1 maximum gain 6.7 dbvrms min imum g ain 6 .7 dbvrms digital logic senb, dena, denb, bit0, bit1, bit2, bit3, bit4, bit5 input high voltage , v inh 2.2 v input low voltage , v inl 1.2 v input capacitance, c in 1 pf input resistance, r in 50 k spi interface timing senb = high f sclk serial clock frequency (maximum) 44.4 mhz t 1 cs rising edge to first sclk rising edge (minimum) 7.5 ns t 2 sclk high pulse width (minimum) 7.5 ns t 3 sclk low pulse width (minimum) 15 ns t 4 sclk falling edge to cs low (minimum) 7.5 ns t 5 sdat setup time (minimum) 7.5 ns t 6 sdat hold time (minimum) 15 ns parallel port timing senb = low t 7 dena/denb high pulse width (minimum) 7.5 ns t 8 dena/denb low pulse width (minimum) 15 ns t 9 bitx setup time (minimum) 7.5 ns t 10 bitx hold time (minimum) 7.5 ns power and enable vpsia, vpsib, vpsoa, vpsob, icom, ocom, enbl supply voltage range 4.75 5.25 v total supply current enbl = 5 v 180 ma disable current enbl = 0 v 3.2 ma disable threshold 1.65 v enable response time delay following high - to - low transition until device meets full specifications 150 ns disable response time delay following low- to - high transition until device produces full attenuation 3 s 1 to convert to dbm for a 200 load impedance , add 7 db to the dbvrms value .
data sheet ad8366 rev. b | page 5 of 28 parallel and serial interface timing sclk cs senb b-lsb b-msb a-lsb x x always high sdat t 5 t 6 t 1 t 2 t 3 t 4 a-msb 07584-003 figure 2. spi port timing diagram t 9 t 7 t 8 t 10 gain a, gain b always low dena denb bit[5:0] senb gain a gain b 07584-004 figure 3. parallel port timing diagram
ad8366 data sheet rev. b | page 6 of 28 absolute maximum rat ings table 2. parameter rating supply voltages , vpsi x and vpsox 5.5 v enbl, senb, dena, denb, bit0, bit1, bit2, bit3, bit4, bit5 5.5 v ippa, ipma, ippb, ipmb 5.5 v oppa, opma, oppb, opmb 5.5 v ofsa, ofsb 5.5 v deca, decb, vcma, vcmb, ccma, ccmb 5.5 v internal power dissipation 1. 4 w ja (with pad soldered to board) 45.4 c/w maximum junction temperature 150 c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering , 60 sec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet ad8366 rev. b | page 7 of 28 pin configuration and function descripti ons notes 1. the exposed pad must be connected to ground. vpsia ippa ipma enbl icom ipmb ippb vpsib bit0/cs bit1/sdat bit2/sclk bit3 ocom bit4 bit5 dena deca ofsa ccma vcma vpsoa oppa opma senb decb ofsb ccmb vcmb vpsob oppb opmb denb 2423 22 21 20 19 18 17 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 3231 30 29 28 27 26 25 ad8366 top view (not to scale) 07584-028 figure 4 . pin configuration table 3 . pin function descriptions pin no. mnemonic description 1, 8, 13, 28 vpsia, vpsib, vpsob, vpso a input and output stage positive supply voltage (4. 7 5 v to 5. 2 5 v). 2, 3, 6, 7 ippa, ipma , ipmb, ippb differential inputs . 4 enbl chip enable. pull this pin high to enable. 5, 20 icom, ocom input and output ground pins . connect th ese pin s via the lowest possible impedance to ground . 9, 32 decb , deca v pos /2 reference decoupling node . connect a decoupling capacitor from these nodes to ground . 10, 31 ofsb, ofsa output offset correction loop compensation. connect a capacitor from these nodes t o ground to enable the correction loop . tie this pin to ground to disable. 11, 30 ccmb, ccma connect these nodes to g round. 12, 29 vcmb, vcma output common -m ode setpoint. these pins d efault to v pos /2 if left open . drive these pins from a low impedance source to change the output common - mode voltage. 14, 15, 26, 27 oppb, opmb , opma, oppa differential outputs . 16, 17 denb, dena data e nable. pull these pins high to address each or both channels for parallel gain programming. these pins are not used in serial mode. 18, 19, 21, 22, 23, 24 bit5, bit4, bit3, bit2 /sclk , bit1 /sdat , bit0 /cs parallel data path (w hen senb is low ) . when senb is high, bit0 becomes a chip select ( cs ), bit1 becomes a serial data input ( sdat ) , and bit2 becomes a serial clock ( sclk ) . bit3 to bit5 are not used in serial mode . 25 senb serial interface e nable. pull this pin high for serial gain programming mode and pull this pin low for parallel gain programming mode . epad the exposed pad must be connected to ground .
ad8366 data sheet rev. b | page 8 of 28 typical performance characteristics v s = 5 v, t a = 25c, z s = 200 ?, z l = 200 ?, f = 10 mhz, unless otherwise noted . 4 6 8 10 12 14 16 18 20 22 0 5 10 15 20 25 30 35 40 45 50 55 60 gain (db) 07584-005 gain code t a = +85c t a = +25c t a = C40c figure 5 . gain vs. gain code at 500 khz, 3 mhz, 10 mhz, and 50 mhz 07584-007 C10 5 0 5 10 15 20 25 100k 1m 10m 100m 1g gain channe l a, gain channe l b (db) frequenc y (hz) gain code 32 gain code 16 gain code 00 gain code 48 gain code 63 figure 6 . frequency response vs. gain code 07584-008 C1.0 C0.9 C0.8 C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 10 20 30 40 50 60 amplitude mism a tch (db) gain code figure 7 . channel a -to- channel b amplitude mismatch vs. gain code, 2 v p - p output 07584-006 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 0.3 0.4 0.5 0 5 10 15 20 25 30 35 40 45 50 55 60 gain error (db) gain code frequency = 3mhz frequency = 50mhz t a = +85c t a = +25c t a = C40c figure 8 . gain error vs. gain code, error normalized to 10 mhz 07584-017 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 C40 C30 C20 C10 0 10 20 30 40 50 60 70 80 gain (db) tempera ture ( c) figure 9 . gain vs. temper ature at maximum gain at 10 mhz 07584-009 C1.0 C0.9 C0.8 C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 10 20 30 40 50 60 phase mism a tch (degrees) gain code figure 10 . channel a -to- channel b phase mismatch vs. gain code, 2 v p - p output
data sheet ad8366 rev. b | page 9 of 28 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 50 55 60 op1db (db v rms) op1db (dbm) gain code t a = +85c t a = +25c t a = C40c 07584-030 figure 11 . op1db vs. gain code at 500 khz, 3 mhz, 10 mhz, and 50 mhz 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 55 60 oip3 (db v rms) oip3 (dbm) gain code t a = +85c t a = +25c t a = C40c frequency = 10mhz frequency = 50mhz 07584-039 figure 12 . oip3 vs. gain code at 10 mhz and 50 mhz frequency, 2 v p - p composite output C1 10 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 5 10 15 20 25 30 35 40 45 50 55 60 imd3 (dbc) gain code t a = +85c t a = +25c t a = C40c frequency = 10mhz frequency = 50mhz 07584-042 figure 13 . two - tone output imd3 vs. gain code at 10 mhz and 50 mhz frequency, 2 v p - p composite output 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 op1db (db v rms) op1db (dbm) frequenc y (mhz) gain code 0 gain code 63 t a = +85c t a = +25c t a = C40c 07584-029 figure 14 . op1db vs. frequency at gain code 0 and gain code 63 0 5 10 15 20 25 30 35 40 45 50 0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 oip3 (dbm) frequenc y (mhz) gain code 32 gain code 0 t a = +85c t a = +25c t a = C40c channel a channel b 07584-041 gain code 63 figure 15 . oip3 vs. frequency, gain code 0, gain code 32, and gain code 63, 2 v p - p composite output C1 10 C90 C70 C50 C30 C10 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 imd3 (dbc) frequenc y (mhz) gain code 0 t a = +85c t a = +25c t a = C40c channel a channel b gain code 63 gain code 32 07584-040 figure 16 . two - tone output imd3 vs. frequency at gain code 0, gain code 32, and gain code 63, 2 v p - p composite output
ad8366 data sheet rev. b | page 10 of 28 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 55 60 oip2 (db v rms) oip2 (dbm) gain code t a = +85c t a = +25c t a = C40c frequency = 10mhz frequency = 50mhz 07584-044 figure 17 . oip2 vs. gain code at 10 mhz and 50 mhz frequency, 2 v p - p composite output C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 5 10 15 20 25 30 35 40 45 50 55 60 imd2 (dbc) gain code t a = +85c t a = +25c t a = C40c frequency = 10mhz frequency = 50mhz 07584-045 figure 18 . two - tone output imd2 vs. gain code at 10 mhz and 50 mhz frequency, 2 v p - p composite output C120 C1 10 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 1 10 100 1000 hd2, hd3 (dbc) frequenc y (mhz) hd2hd3 gain code 0 gain code 32 gain code 63 07584-032 figure 19 . harmonic distortion vs. frequency at gain code 0, gain code 32, and gain code 63, 2 v p - p output 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 oip2 (dbm) frequenc y (mhz) t a = +85c t a = +25c t a = C40c channel a channel b 07584-043 gain code 0 gain code 63 figure 20 . oip2 vs. frequency at gain code 0 and gain code 63, 2 v p - p composite output C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 imd2 (dbc) frequenc y (mhz) t a = +85c t a = +25c t a = C40c channel a channel b gain code 63 gain code 0 07584-052 figure 21 . two - tone output imd2 vs. frequency, gain code 0 and gain code 63, 2 v p - p composite output C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 C1 10 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 hd3, gain code 0 (dbc) hd2, gain code 0 (dbc) vcma, vcmb (v) t a = +85c t a = +25c t a = C40c channel a channel b 07584-023 figure 22 . hd3/hd2 vs. v ocm at 10 mhz, gain code 0, 2 v p - p output
data sheet ad8366 rev. b | page 11 of 28 0 10 20 30 40 50 60 C3 C2 C1 0 1 2 3 4 5 oip3 (dbm) p out per t one (dbm) 07584-055 gain code 0 gain code 63 t a = +85c t a = +25c t a = C40c figure 23 . oip3 vs. output power (p out ) at minimum and maximum gain codes, 10 mhz frequency 0 10 20 30 40 50 60 70 80 90 100 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 oip2 (dbm) p out per t one (dbm) gain code 0 gain code 63 t a = +85c t a = +25c t a = C40c 07584-060 figure 24 . oip2 vs. output power (p out ) at minimum and maximum gain codes, 10 mhz frequency C 110 C105 C100 C95 C90 C85 C80 C75 C70 C65 C60 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 hd2 (dbc) p out (dbm) t a = +85c t a = +25c t a = C40c 07584-053 gain code 0 gain code 63 figure 25 . hd2 vs. output power (p out ) at gain code 0 and gain code 63, 10 mhz frequency C1 10 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 C3 C2 C1 0 1 2 3 4 5 imd3 (dbc) p out per t one (dbm) gain code 0 gain code 63 t a = +85c t a = +25c t a = C40c 07584-061 figure 26 . imd3 vs. output power (p out ) at minimum -to- maximum gain codes, 10 mhz frequency p out per t one (dbm) C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 imd2 (dbc) gain code 0 gain code 63 t a = +85c t a = +25c t a = C40c 07584-062 figure 27 . imd2 vs. output power (p out ) at minimum and maximum gain codes, 10 mhz frequency C120 C1 15 C1 10 C105 C100 C95 C90 C85 C80 C75 C70 C65 C60 C5 C4 C3 C2 C1 0 1 2 3 4 5 hd3 (dbc) p out (dbm) t a = +85c t a = +25c t a = C40c 07584-054 gain code 0 gain code 63 figure 28 . hd3 vs. output power (p out ) for gain c ode 0 and gain code 63, 10 mhz frequency
ad8366 data sheet rev. b | page 12 of 28 100 120 140 160 180 200 220 240 260 280 300 0 5 10 15 20 25 30 35 40 45 50 55 60 supply current (ma) gain code 07584-038 t a = +85c t a = +25c t a = C40c figure 29 . supply current vs. gain code at 10 mhz 07584-0 11 10 12 14 16 18 20 22 24 26 28 30 0 5 10 15 20 25 30 35 40 45 50 55 60 noise figure (db) gain code channel b, frequency = 0.5mhz channel a, frequency = 0.5mhz channel b, frequency = 3mhz channel a, frequency = 3mhz channel b, frequency = 10mhz channel a, frequency = 10mhz channel b, frequency = 50mhz channel a, frequency = 50mhz figure 30 . noise figure vs. gain code at 0 .5 m hz, 3 mhz, 10 mhz, and 50 mhz 07584-013 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 180 190 200 210 220 230 240 250 260 270 280 0 20 40 60 80 100 120 140 160 180 200 input ca p aci t ance (pf) input resis t ance ( ? ) frequenc y (mhz) channel a: r in , gain code 0 channel a: r in , gain code 32 channel a: r in , gain code 63 channel a: r in , gain code 0 channel b: r in , gain code 32 channel b: r in , gain code 63 channel a: c in , gain code 0 channel a: c in , gain code 63 channel b: c in , gain code 32 channel a: c in , gain code 32 channel b: c in , gain code 0 channel b: c in , gain code 63 figure 31 . differential parallel input resistance and capacitance vs. frequency 07584-010 10 15 20 25 30 35 40 45 50 55 60 0.1 1 10 100 1000 noise spectra l densit y (nv/ hz ) frequenc y (khz) channel a channel b gain code 63 gain code 47 gain code 48 gain code 31 gain code 32 gain code 15 gain code 16 gain code 0 figure 32 . noise spectral density vs. frequency 07584-012 10 12 14 16 18 20 22 24 26 28 30 noise figure (db) channel a channel b 0.1 1 10 100 1000 frequenc y (khz) gain code 0 gain code 15 gain code 16 gain code 31 gain code 32 gain code 47 gain code 48 gain code 63 figure 33 . noise figure vs. frequency 07584-014 4.5 4.8 5.1 5.4 5.7 6.0 6.3 6.6 6.9 7.2 7.5 10 13 16 19 22 25 28 31 34 37 40 0 20 40 60 80 100 120 140 160 180 200 output inductnace (nh) output resis t ance ( ? ) frequenc y (mhz) channel a: r out , gain code 0 channel a: r out , gain code 32 channel a: r out , gain code 63 channel b: r out , gain code 32 channel a: l out , gain code 0 channel a: l out , gain code 63 channel b: l out , gain code 32 channel a: l out , gain code 32 channel b: l out , gain code 0 channel b: l out , gain code 63 channel a: r out , gain code 0 channel b: r out , gain code 63 figure 34 . differential series output resistance and inductance vs. frequency
data sheet ad8366 rev. b | page 13 of 28 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 psrr (db) frequenc y (mhz) psrr gain code 0 psrr gain code 63 07584-036 figure 35 . power supply rejection ratio (psrr) vs. frequency 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 grou p del ay (ns) frequenc y (mhz) gain code 32 gain code 0 gain code 63 07584-021 figure 36 . group delay vs. frequency at gain code 0, gain code 32, and gain code 63 C120 C100 C80 C60 C40 C20 0 1 10 100 1000 isolation (db) frequenc y (mhz) driven channel at gain code 0 measured channel at gain code 63 measured channel at gain code 32 measured channel at gain code 0 07584-034 figure 37 . channel -to- channel isolation vs. frequency, channel a driven, channel b measured 0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 0 5 10 15 20 25 30 35 40 45 50 55 60 sfdr (db) gain code frequency = 10mhz frequency = 50mhz t a = +85c t a = +25c t a = C40c 07584-037 figure 38 . sfdr vs. gain code at 10 mhz and 50 mhz, 1 hz an alysis bandwidth 07584-016 0 10 20 30 40 50 60 70 80 90 1m 10m 100m 1g cmrr (db) frequenc y (hz) gain code 32 gain code 63 gain code 0 figure 39 . common - mode rejection ratio (cmrr) vs. frequency 0 1 10 100 1000 forward leakage (dbm) frequenc y (mhz) p in = +10dbm p in = +5dbm p in = 0dbm p in = C5dbm p in = C10dbm C20C40 C60 C80 C100C120 C140 C160 07584-031 figure 40 . forward leakage vs. frequency, part disabled
ad8366 data sheet rev. b | page 14 of 28 C1.2 C1.0 C0.8 C0.6 C0.4 C0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 C5C4C3C2C1012345 output voltage (v) time (ns) 10pf 0pf 07584-067 figure 41. large signal pulse response, gain code 0, input signal 1.2 v p-p, 0 pf and 10 pf capacitive loading conditions ?? 5gs/s 100k pts a ch1 1.60v 2 1 07584-065 ch1 1v ch2 100mv m1s t 4.02s figure 42. enbl time domain response frequency (mhz) C120 C100 C80 C60 C40 C20 0 0.1 1 10 100 1000 s12 mag (db) 07584-033 figure 43. reverse isolation (s12) vs. frequency C1.2 C1.0 C0.8 C0.6 C0.4 C0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 C5C4C3C2C1012345 output voltage (v) time (ns) 10pf 0pf 07584-068 figure 44. large signal pulse response, gain code 63, input signal 240 mv p-p, 0 pf and 10 pf capacitive loading conditions ch3 50mv ch4 1v ?? m 200ns 250ms/s 4.0ns/pt a ch4 2.48v 3 07584-064 figure 45. gain step time domain response, minimum-to-maximum gain (time scale 200 ns/division), ch4 = digital control inputs
data sheet ad8366 rev. b | page 15 of 28 circuit description the ad8366 is a dual , differential , digitally controlled vga with 600 mhz of 3 db bandwidth and a gain range of 4.5 db to 20. 25 db adjustable in 0.25 db steps. using a proprietary variable gain architecture, the ad8366 is able to achieve excel len t linearity ( 45 dbm) and noise performance ( 11.7 nv/ hz ) at 10 mhz at minimum gain . intended for use in direct conversion systems, the part also includes dc offset correction that can be disabled easily by grounding either ofsa or ofsb. in addition, the part off ers an adjustable output common - mode range of 1.6 v to 3 v. the main signal path is shown in figure 46 . it consists of an input transconductance, a variable - gain cell, and an output transimpedance amplifier. 100?100? 12.5? 12.5? v ariable curren t -gain st age output buffer z a i virtua l ground virtua l ground in p inm out p outm 07584-071 figure 46 . main signal path the input transconductance provides a broadband 200 ? differential termination and converts the input voltage to a current. this current is fed into the variable current - gain cell. the output of this cell goes into the transimpedance stage, which gen erates the output voltage. the transimpedance is fixed at 500 ?, with a roughly 25 ? differential output impedance. i nputs the inputs to the digitally - controlled vgas in the ad8366 are differential and can be either ac - or dc - coupled . the ad8366 synthesizes a 200 ? (differential) input impedance, with a return loss (re: 200 ?) of better than 10 db to 200 mhz. the nominal common - mode input voltage to the part is v pos /2, but the ad8366 can be dc - cou pled to parts with lower common modes if the se parts can sink current. the amount of current sinking required depends on the input common - mode level and is given by i sink ( per leg ) = ( v pos /2 ? v icm )/100 the i nput common - mode range is 1.5 v to v pos /2 . o utputs the outputs of the digitally - controlled vgas are differential and can be either ac - or dc - coupled. the ad8366 synthesizes a 25 ? differential output impedance, with a return loss (re: 25 ?) of better than 10 db to 120 mhz . the nominal common - mode output voltage is v pos /2 ; however, it can be lowered or raised by driving the vcma or vcmb pins. output differential offset correction t o prevent significant levels of offset from appearing at the outputs of the ad8366, each digitally controlled vga has a differential offset correction loop, as s hown in figure 47 . this loop senses any differential offset at the output and corrects fo r it by injecting an opposi ng current at the input differential ground. the lo op is able to correct for input dc offsets of up to 20 m v. becaus e the loop automatically null s out any dc or low frequency offset, the effect of the loop is to introduce a high - pass corner into the transfer function of the digitally controlled vga . the location of this high - pass corner depends on both the gain setting and the value of the capacitor connected to the ofs x pin (ofsa for d v ga a and ofsb for d vg a b ) and is given by ( ) ( ) ( ) 10 2 4000 1.037 4300 khz ,3 + + = ofs gc hp db c f where: gc is the gain code (a value from 0 to 63) . c ofs is the value of the capacitance connected to ofsa or ofsb , in picofarads (pf). the offset correction loop can be disabled by grounding either ofsa or ofsb. g m1 g m2 inp inm offset compensation loop v ariable-gain st age output buffer z a i out p outm c ofs 07584-073 figure 47 . differential offset correction loop output common - mode co ntrol t o interface to adcs that require different input common - mode voltages, the ad8366 has an adjustable output common - mode level. the output common - mode level is normally set to v pos /2 ; however, it can be changed between 1.6 v and 3 v by driving the vcm a pin or the vcmb pin. the input equivalent circuit for the vcma pin is shown in figure 48 ; the vcmb pin has the same input equivalent circuit. 4k? 500? v pos /2 vcma 07584-072 figure 48 . input equivalent circuit for vcma
ad8366 data sheet rev. b | page 16 of 28 gain control interfa ce the ad8366 provides two methods of digital gain control: serial or parallel. when the senb pin is pulled low , the part is in parallel gain control mode. in this mode, the two digitally controlled vgas can be programmed simultaneously, or one at a time, depending on the levels at dena and denb. if the senb pin is pulled high , the part is in serial gain control mode, with pin 24, pin 23, and pin 22 corresponding to the cs, sdat , and sclk signals, respectively. the voltage gain of the ad8 366 is well approximated by gain (db) = gaincode 0.253 + 4.5 note that at several major transitions (15 to 16, 31 to 3 2, and 47 to 48), the gain changes significantly less (0 db step ) or significantly more (0.5 db step ) than the desired 0.25 db step. this is inherent in the design of the part and is related to the p artitioning of the variable gain block into a fine - gain and a coarse - gain section. C1.0 C0.8 C0.6 C0.4 C0.2 0 0.2 0.4 0.6 0.8 1.0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 0 5 10 15 20 25 30 35 40 45 50 55 60 gain ste p error (db) gain (db) gain code 07584-063 figure 49 . gain and gain step error vs. gain code at 10 mhz
data sheet ad8366 rev. b | page 17 of 28 applications information basic connections figure 50 shows the basic connections for operating the ad8366 . a volt age from 4.75 v to 5.25 v must be applied to the sup ply pins. each s upply pin must be decoupled with at least one low inductance, surface - mount cerami c capacitor of 0.1 f placed as close as possible to the device. the differential input impedance is 200 ? and sits at a no minal common - mode voltage of v pos /2 . the inputs can be dc - coupled or ac - coupled. if using direct dc coupling, the common - mode voltage, v cm , can range from 1.5 v to v pos /2 . the output buffers of the ad8366 are low impedance around 25 ? designed to drive adc inputs. the output co mmon - mode voltage defaults t o v pos /2 ; h owever , it can be adjusted by applying a desired external voltage to v cm a/ vcm b . the common - mode voltage can be adjusted from 1.6 v to 3.0 v without significant harmonic distortion degradation. to enable the ad8366, the enbl pin must be pulled high. taking enbl low disables the device, reducing current consumption to approximately 3 ma at ambient temperature. vpsia ippa ipma enbl icom ipmb ippb vpsib bit0/cs bit1/sdat bit2/sclk bit3 ocom bit4 bit5 dena decb ofsb ccmb vcmb vpsob oppb opmb denb deca ofsa ccma vcma vpsoa oppa opma senb vpos ad8366 vpos 0.01f 0.01f 0.01f 8200pf 8200pf 0.01f 0.01f 0.01f 0.01f vpos 0.1 f 0.1 f vpos 0.1 f 0.1 f vpos 0.1 f 0.1 f parallel/serial control interface (pci) channel a output channel b output channel a input channel b input 07584-046 figure 50 . basic connections
ad8366 data sheet rev. b | page 18 of 28 rf lo matching network pad filter balun lc low- pass filter lc low- pass filter lc low- pass filter lc low- pass filter adl5523 adl5380 ad8366 adl5523 0 90 adf4350 to adc 07584-047 figure 51 . direct conversion receiver block diagram direct conversion receiver design a direct conversion receiver directly demodulates an rf modu lated carri er to baseband frequencies, where the signals can be detected and the conveyed information recovered. eliminating the if stages and directly converting the signal to effectively zero if results in reduced component count. the i mage problems associated with the traditional superheterodyne architectures can be ignored as well. however , there are different challenges associated with direct conversion that include lo leakage, dc offsets , q uadrature i mperfections , and image r ejection. lo leakage causes self mixing that results in squaring of the lo waveform which generates a dc offset tha t falls in band for the direct conversion receiver. residual dc offsets create a similar interfering signal that falls in band. i/q amplitude and phase m ismatch lead to degraded snr performance and poor image rejection in the direct conversion system . figure 51 shows the block diagram for a direct conversion receiver system. quadrature e rrors and image rejection an overall rf - to - baseb and evm performance was measured with the adl5380 iq demodulator preceding the ad8366 , as s hown in figure 56 . in this setup , no lc low -p ass filters were used between the adl5380 and ad8366. a 1900 mhz w - cdma rf signal with a 3.84 mhz symbol rate was used. the local o scillator (lo) is set at 1900 mhz to obtain a z ero if baseband signal. the gain of the ad8366 is set to maximum gain (~20. 25 db) . figure 52 shows the snr vs. the input power of the cascaded system for a 5 mhz analysis bandwidth. the broad input power range over which the system exhibits strong snr performance reflects the superior dynamic range of the ad8366 . 0 5 10 15 20 25 30 35 40 45 C75 C65 C55 C45 C35 C25 C15 C5 5 snr (db) input power (dbm) 07584-048 figure 52 . snr vs. rf input power level the image rejection ratio is the ratio of the intermedia te frequency (if) signal level produced by the desired input frequency to that produced by the image frequency. the image rejection ratio is expressed in decibels (db). appropriate image rejection is criti cal because the image power can be much higher than that of the desired signal, thereby plaguing the downconver sion process. amplitude and phase balance between the i/q channels are critical for high levels of image rejection. image rejection of greater than 47 db was measured for the combined adl5380 and the ad8366 for a 5 mhz baseband frequency , as seen in figure 53 . this level of image rejection corresponds to a 0.5 phase mismatch and a 0.05 db of amplitude mismatch for the com bined adl5380 and ad8366. looking back to figure 7 and figure 10 , the ad8366 exhibits only 0.05 db of amplitude mismatch and 0.05 o of phase mismatch , thus implying that the ad8366 does not introduce additional amplitude and phase imbalance. 25 30 35 40 45 50 55 900 1500 1300 1100 1700 1900 2100 2300 2500 2700 2900 rf fre qu ency (mhz) image rejection (db) 07584-049 figure 53 . image rejection vs. rf frequency
data sheet ad8366 rev. b | page 19 of 28 low frequency imd3 p erformance to measure the imd3 data at low frequencies, wideband transformer baluns from north hills signal processing corp. were used, specifically the 0301bb and the 0520bb. figure 55 shows the imd3 performance vs . frequency for a 2 v p- p composite output. the imd3 performance was also measured for the combined adl5380 and ad8366 system, as shown in figure 56 , with an fft spectrum analyzer. an fft spectrum analyzer works very similar to a typical adc, the input signal is digitized at a high sampling rate that is then passed through an antialiasing filter. the resulting signal is transformed to the frequency domain using f ast fourier t ransforms (fft). the single - ended rf signal from the source generator is converted to a differentia l signal using a balun that gets demodulated and down converted to differential if signals through the adl5380 . this differential if signal drive s the ad8366, thus eliminating the need for low frequency baluns. figure 54 shows the imd3 performance vs . frequency over the 500 khz to 5 mhz range for min imum and max imum gain code setting on the ad8366. during the measurements , the output was set to 2 v p - p composite . C90 C80 C70 C60 C50 C40 C30 C20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 imd3 (dbc) frequenc y (mhz) gc63 gc0 07584-018 figure 54 . system imd3 vs. frequency , 2 v p- p c omposite at the o utput of the ad8366 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 55 60 imd3 (dbc) oip3 (dbm) gain code frequency = 1mhz frequency = 3mhz 07584-035 figure 55 . oip3 on low frequency, 2 v p - p composite
ad8366 data sheet rev. b | page 20 of 28 v pos 0.1 f 100p f v pos 0.1 f 100p f lo balun 100pf 100pf v pos balun rfin 100pf 100pf vpos 0.1 f 100p f 1 24 23 22 21 20 19 7 8 9 10 11 12 23 4 5 6 18 17 16 15 14 13 vcc gnd rfip rfin gnd adj gnd gnd qhi qlo gnd vcc enbl gnd loip loin gnd nc gnd gnd ihi ilo gnd vcc adl5380 ad8366 bit0 bit1 bit2 bit3 ocom bit4 bit5 dena vpsia ippa ipma enbl icom ipmb ippb vpsib deca ccma vpsoa opma ofsa vcma oppa senb decb ccmb vpsob opmb ofsb vcmb oppb denb v pos 0.01 f 0.1 f 0.01 f v pos v pos 0.1 f 0.1 f parallel/serial control interface v pos 0.1 f 0.01 f 0.1 f 0.01 f 0.01 f c ofs v pos 0.01 f 200? 200? q channel c ofs 07584-050 i channel figure 56 . adl5380 and ad8366 interfa ce block diagram
data sheet ad8366 rev. b | page 21 of 28 baseband interface in most direct - conversion receiver designs, it is desirable to select a wanted carrier within a specified band. the desired channel can be demodulated by tuning the lo to the appropriate carrier fre quency. if the desired rf band contains multiple carriers of interest, the adjacent carriers would also be down converted to a lower if frequency. these adjacent carriers can be a problem if they are large relative to the desired carrier because they can overdrive the baseband signal detection circuitry. as a result, it is often necessary to insert a filter to provide sufficient rejection of the adjacent carriers. it is necessary to consider the overall source and load imped ance presented by the ad8366 and the adc input to design the filter network. the differential baseband outp ut impedance of the ad8366 is 25 ? and is designed to drive a high impedance ad c input. it may be desirable to terminate the adc inpu t down to the lower impedance by using a terminating res istor, such as 500 ?. the terminating resistor helps to better define the input impedance at the adc input at the cost of a slightly reduced gain . the order and type of filter network depends on the desired hi gh frequency rejection required, pass - band ripp le, and group delay. figure 57 shows the schematic for a typical fourth - order , chebyshev , l ow -p ass filter. table 4 shows the typical values of the filter components for a fourth - order , chebyshev , low - pass filter with a differential source impedance of 25 and a differential load impedance of 200 . l1 l2 c1 l3 l4 c2 z load z source 07584-051 figure 57 . schematic of a fourth - order, chebyshev, low - pass filter table 4 . typical v alues for fourth - order, chebyshev, low - pass filter 3 db corner (mhz) z source () z load () l1 ( h) l2 ( h) l3 ( h) l4 ( h) c1 (pf) c2 (pf) 5 25 200 6.6 6.6 6.0 6.0 220 180 10 25 200 3.3 3.3 3 3 110 90 28 25 200 1.2 1.2 1 1 39 33
ad8366 data sheet rev. b | page 22 of 28 characterization setups figure 58 and figure 59 are characterization setups used extensively to characterize the ad8366. characterizati on was done on single - ended and differential evaluation board s . the bulk of the characterization w as done us ing an automated vee program to control the equipment as shown in figure 58 . this setup was used to measure p1db, oip3, oip2, imd2, imd3, harmonic distortion, gain, gain error, supply current , and noise density. all measurements were done with a 200 ? load. all balun, out put matching network , and filter losses were de - embedded. gain error was measured with constant input power. a ll other measurements were done on 2 v p- p (4 dbm , re : 200 ? ) on the output of the device under test ( dut ) , and 2 v p-p composite output for two - tone measurements. to measure harmonic distortion , band - pass and band - reject filters were used on the input and output of the dut. figure 59 shows the setup used to make differential measurements. all measurements on this setup were done in a 50 ? system and post processed to reference the measurements to a 200 ? system. gain and phase mismatch we re measured with 2 v p- p on the output, and small signal frequency response s w ere measured with ? 30 dbm on the input of the dut .
data sheet ad8366 rev. b | page 23 of 28 agilent 34980a multifunction switch (with 34950 and 34921 modules) agilent 34401a dmm (in dc i mode for supply current measurement) agilent e3631a power supply band pass agilent e8251d signal generator agilent e8251a signal generator agilent e4440a spectrum analyzer combiner ieee ieee ieee ieee ieee ieee rf switch matrix keithley rf switch matrix keithley ad8366 evaluation board band reject ieee ieee 07584-069 ch1 rf in ch2 rf in ch1 rf out ch2 rf out figure 58. characterization setup, single-ended measurements
ad8366 data sheet rev. b | page 24 of 28 ad8366 evaluation board ch1 op ch1om ch2 op ch2om ch2 ip ch2 im ch2 ip ch2 im rohde & schwarz zva8 rf switch matrix keithley agilent e3631a power supply 07584-070 figure 59. characterization setup, differential measurements
data sheet ad8366 rev. b | page 25 of 28 evaluation board the schematic for the ad8366 evaluation board is shown in figure 60 . the board can be used for single - ended or differential baseband analysis. the default configuration of the board is for single - ended baseband analysis. c33 s4 ad8366 dena vpsia ippa ipma enbl icom ipmb ippb vpsib deca ccma vpsoa opma ofsa vcma oppa senb decb ccmb vpsob opmb ofsb vcmb oppb denb bit0 bit1 bit2 bit3 ocom bit4 bit5 r30 r29 r34 r69 r65 r67 r71 r70 r35 r39 t3 c26 c24 r16 r19 r20 r58 r47 r46 r63 r62 r21 r15 t2 c5 c21 r13 r12 r17 r48 r44 r45 r54 r50 r18 r14 t1 c20 c18 r33 r31 r36 r72 r68 r80 r74 r73 r37 r38 t4 c27 c25 r40 vpsi_a s9 r61 vpsi_a s2 r41 vpsi_a s6 r42 vpsi_a s8 r43 vpsi_a s3 r26 r32 vpsi_a c11 c2 c29 s5 r53 vpsi_a s10 r64 bit2 vpsi_a c31 s7 r57 vpsi_a vpso_a vcma vpso_b vcmb c12 c3 c10 s12 c9 enbl vpsi_b vpsi_a u1 bit2 c23 r6 c16 vpso_b r5 c15 vpso_a vpos r4 c14 vpsi_b r3 c13 c1 vpsi_a s1 vpsi_a r79 c30 enbl r10 vpsi_a r22 c22 vcma r24 vpsi_b r28 c28 vcmb 07584-056 s11 figure 60 . evaluation board schematic
ad8366 data sheet rev. b | page 26 of 28 07584-059 figure 61. ad8366 evaluation board printed circuit board (pcb), top side 07584-058 figure 62. ad8366 evaluation board pcb, bottom side table 5. evaluation board configuration options components function default conditions c1, c13 to c16, r3 to r6 power supply decoupling. nominal supply decoupling consists of a 0.1 f capacitor to ground followed by 0.01 f capacitors to ground positioned as close to the device as possible. c1 = 0.1 f (size 0603), c13 to c16 = 0.01 f (size 0402), r3 to r6 = 0 (size 0603) t1, t2, c5, c18, c20, c21, r12 to r21, r44 to r48, r50, r54, r58, r62, r63 input interface. the default configuration of the evaluation board is for single-ended operation. t1 and t2 are 4:1 impedance ratio baluns to transform a 50 single-ended input into a 200 balanced differential signal. r12 to r14 and r15, r16, and r19 are populated for appropriate balun interface. r44 to r48 and r50, r54, r58, r62, and r63 are provided for generic placement of matching components. c5, c18, c20, and c21 are balun decoupling capacitors. r17, r18, r20, and r21 can be populated with 0 , and the balun interfacing resistors can be removed to bypass t1 and t2 for differential interfacing. t1, t2 = adt4-6t+ (mini-circuits), c5, c20 = 0.1 f (size 0402), c18, c21 = do not install, r12 to r16, r19, r44 to r47 = 0 (size 0402), r17, r18, r20, r21,r48, r50, r54, r58, r62, and r63 = open (size 0402) t3, t4, c24 to c27, r29 to r31, r33 to r39, r65, r67 to r74, r80 output interface. the default configuration of the evaluation board is for single-ended operation. t3 and t4 are 4:1 impedance ratio baluns to transform a 50 single-ended output into a 200 balanced differential load. r29 to r31, r33, r38, and r39 are populated for appropriate balun interface. r65, r67 to r74, and r80 are provided for generic placement of matching components. c24, c25, c26, and c27 are balun decoupling capacitors. r34 to r37 can be populated with 0 , and the balun interfacing resistors can be removed to bypass t3 and t4 for differential interfacing. t3, t4 = adt4-6t+ (mini-circuits), c24, c25 = 0.1 f (size 0402), c26, c27 = do not install, r29 to r31, r33, r38, r39, r65, r67, r68, r80 = 0 (size 0402), r34 to r37, r69 to r74 = open (size 0402)
data sheet ad8366 rev. b | page 27 of 28 components function default conditions s1, s5, s7, r53, r57, r79, c29, c30, c31 enable i nterface includes d evice enable and d ata enable . device e nable. the ad8366 is enabled by applying a logic high voltage to the enbl pin. the device is enabled when the s1 switch is set in the down position ( high ), connecting the enbl pin to vpsi_a . data e nable. dena and denb are used to enable the data path for channel a and channel b , respectively. channel a is enabled when the s5 switch is set in the down position ( high ), connecting the dena pin to vpsi_a . likewise, channel b is enabled when the s7 switch is set in the down position ( high ), connecting the denb pin to vpsi_a . both channels are disabled by setting the switches to the up position , connecting the dena and denb pins to gnd. s1, s5, s7 = installed , r53, r57 = 5.1 k (size 0603) , r79 = 10 k (size 0402) , c30 = 0.01 f (size 0402) , c29, c31 = 1500 pf (size 0402) s2, s3, s4, s6, s8, s9, s10 r26, r32, r40 to r43, r61, r64 , c23, c33 , u1 serial/ parallel interface control . senb is used to set the data control either in parallel or serial mode. the parallel i nterface is enabled when s4 is in the up position ( low ). the s erial interface is enabled when s4 is in the down position ( high ). for senb pulled low , bit0 (s9) sets 0.25 db g ain , bit1 (s2) sets 0.5 db g ain , bit2 ( s3) sets 1 db g ain , bit3 (s6) sets 2 db g ain , bit4 ( s8) sets 4 db g ain , and b it5 (s10) sets 8 db g ain . for senb pulled high , bit0 becomes a chip select (cs), bit1 becomes a serial data input ( sdat ) , and bit2 becomes serial clock ( sclk ) . bit3 to bit5 are not used in serial mode. u1 is used to deglitch the sclk signal . s2, s3, s4, s6, s8, s9, s 10 = installed , r26 = 698 k (size 0603) , r32, r40 to r43, r61, r64 = 5.1 k (size 0603) , c23, c33 = 1500 pf (size 0603) , u1 = sn74lvc2g14 inverter chip s11, s12, c9, c10 dc offset correction loop compensation . the dc offset correction loop is enabled ( high ) with s11 and s12 for c hannel a and c hannel b , respectively , w hen the enabled pins , ofsa/ ofsb, are connected to ground through the c9 and c10 capacitors . wh en disabled ( low ), ofsa/ofsb are connected to ground directly . s11, s12 = installed , c9, c10 = 8200 pf (size 0402) r10, r22, r24, r28, c22, c28 output common - mode setpoint . the output common mode on c hannel a and channel b can be set externally when applied to vcma and vcmb. the resistive change through the potentiometer sets a variable vcma volt age. if left open, the output common mode defaults to v pos /2. r10, r24 = 10 k p otentiometers , r22, r28 = 0 , c22, c28 = 0.1 f (size 0402) c2, c3, c11, c12 r eference output decoupling capacitor to circuit common . c2, c3 = 0.1 f (size 0402) , c11, c12 = 0.01 f (size 0402)
ad8366 data sheet rev. b | page 28 of 28 outline dimensions 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.20 min 2.85 2.70 sq 2.55 compliant to jedec standards mo-220-whhd-2. 08-22-2013-a pkg-004332 figure 63. 32-lead lead frame chip scale package [lfcsp] 5 mm 5 mm body and 0.75 mm package height (cp-32-21) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD8366ACPZ-R7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp] cp-32-21 ad8366-evalz evaluation board 1 z = rohs compliant part. ?2010 C2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07584-0-8/17(b)

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